1. Field of the Invention
The present invention relates to a method of designing a semiconductor integrated circuit device, and to a semiconductor integrated circuit device, and more particularly to a method of designing a semiconductor integrated circuit device capable of reducing overhead such as clock skews and clock jitters when designing a pipeline in an integrated circuit device, and to a configuration of a semiconductor integrated circuit device manufactured according to such designing method.
2. Description of the Background Art
In an LSI large scale integrated circuit), a synchronous multi-stage pipeline for processing/transferring a signal synchronously with a clock signal so as to transfer the signal/data at high speed, is widely used. In constituting such a synchronous multi-stage pipeline, flip-flops or latches are normally used as transfer circuits.
FIG. 9 is a diagram showing an example of the configuration of a two-stage pipeline constituted by flip-flops. In FIG. 9, the two-stage pipeline includes a flip-flop circuit FF01 which transfers an input signal IN synchronously with a clock signal CLK01, a logic circuit LG1 which performs a predetermined logic processing on the signal applied from flip-flop circuit FF01 and outputs a resultant signal, a flip-flop circuit FF02 which transfers the output signal of logic circuit LG1 synchronously with a clock signal CLK02, a logic circuit LG2 which performs a predetermined logic processing on the signal applied from flip-flop FF02 and outputs a resultant signal, and a flip-flop circuit FF03 which transfers the output signal of logic circuit LG2 synchronously with a clock signal CLK03 and generates an output signal/data OUT.
Since logic circuits LG1 and LG2 each perform a logic processing on the received signal for outputting, logic circuits LG1 and LG2 have logic delays L01 and L02 in the propagation of the signals, respectively.
Normally, logic circuits LG1 to LG2 each receive a plurality of signals and performs a logic processing. In the description given hereinafter, though not particularly mentioned, a flip-flop circuit FF transfers one or a plurality of signals. The number of signals transferred by flip-flop circuit FF is determined according to the configuration of a logic circuit LG arranged at the subsequent stage.
Flip-flop circuit FF01 has setup time SUP11 and hold time HLD11 for clock signal CLK01. In addition, flip-flop circuit FF01 has output delay time TPD11 since a trigger edge of clock signal CLK01 is applied until a valid signal is outputted.
Flip-flop circuit FF02 has setup time SUP12 and hold time HLD12 and output delay time TPD12.
Flip-flop circuit FF03 has setup time SUP13 and hold time HLD13 and output delay time TPD13.
Further, fixed skews due to uncertain factors of clock signals, as described later, exist for the clock signals applied to flip-flop circuits FF01 to FF03, respectively.
FIG. 10 is a diagram showing output delay time TPD, setup time SUP and hold time HLD shown in FIG. 9. FIG. 10 shows parameters in a case where flip-flop circuits FF01 to FF03 are each a rising edge trigger type flip-flop that latches and outputs a signal applied at the rising edge of clock signal CLK.
Setup time SUP is a time period for which input signal SIN is kept in a definite state with respect to the rising edge of clock signal CLK. Hold time HLD is a time period required for input signal SIN to be kept in a definite state since the rising edge of clock signal CLK. Output delay time TPD is a time period required since clock signal CLK rises until the output signal SOUT of the flip-flop circuit is made definite.
Normally, setup time SUP is determined under the worst condition for the operating parameters of transistors which constitute a flip-flop. Hold time HLD is calculated using the best operating parameters of the transistors which constitute the flip-flop.
Clock signal CLK has a period TK.
As shown in FIG. 11, clock signals CLK01 to CLK03 are applied from a clock distribution circuit 110 which receives a clock signal CLK0 generated from a clock generation circuit 100. Clock distribution circuit 110 transfers applied clock signal CLK0 to the respective the flip-flop circuits in the pipeline.
Clock generation circuit 100 is constructed by, for example, a PLL (phase locked loop), and generates internal clock signal CLK0 synchronized in phase with an external clock signal such as a system clock. Clock distribution circuit 110 takes various configurations such as a tree-like clock network and a fishbone type clock distribution circuit according to the configuration of this pipeline.
Clock signals CLK01 to CLK03 are transferred through predetermined routes, respectively. Therefore, clock signals CLK01 to CLK03 applied to flip-flop circuits FF01 to FF03 shown in FIG. 9 each have clock signal ambiguities referred to as a skew or a jitter. Thus, clock signals CLK01 to CLK03 are deviated from an ideal edge of a clock signal.
Here, in the description given hereinafter, xe2x80x9cclock skewxe2x80x9d is defined as a spatial clock signal deviation caused by process variation and uneven interconnection in clock distribution circuit 110. Namely, a clock skew indicates the phase deviation of a clock signal caused depending on the positional relationship between each of flip-flop circuits FF01 to FF03 and clock generation circuit 100.
As for the clock skews, fixed factors caused by the unevenness of interconnections and process variations based on layout dependency and uncertain factors dependent on unpredictable process variations and the power supply voltage change, temperature change in clock distribution circuit 110 and other are separately considered. The unevenness of interconnections indicates variations in line width and interconnection length and such. Layout dependent process variations indicate the variations of operating characteristics due to the variations of impurity concentration dependent on the layout in transistors constituting a repeater which is included in clock distribution circuit 110 and which transmits the clock signal.
A xe2x80x9cclock jitterxe2x80x9d is defined as a temporal clock signal deviation caused by the power supply voltage fluctuation, temperature fluctuation or the like in clock generation circuit (PLL) 100. It is, therefore, assumed that only uncertain factors exist for the clock jitters. Since the clock jitter is the temporal deviation of the clock signal, similar clock jitters occur to the respective flip-flop circuits.
Referring back to FIG. 9, a clock skew SKW01 between flip-flop circuits FF01 and FF02 and a clock skew SKW02 between flip-flop circuits FF02 and FF03 are fixed factor components of the clock skew. In addition, a clock skew between flip-flop circuits FF01 and FF03 is denoted by a reference symbol SKWA, which is also a fixed factor component of the clock skew. The fixed factor of the clock skew can take both positive and negative values. The fixed factor (SKW01, SKW02) of a skew of a clock signal delayed in phase from a given clock signal has a positive value (cycle time can be made longer with respect to a logic circuit at the preceding stage). Further, the fixed factor of the skew of a clock signal faster in phase than this clock signal takes a negative value.
The clock skew uncertain factor between flip-flop circuits FF01 and FF02 is equal to that between flip-flop circuits FF02 and FF03, and these factors are each defined to be an absolute value SKWET. This is because they are uncertain factors and the worst case is always supposed.
Furthermore, the clock jitter between flip-flop circuits FF01 and FF02 is equal to that between flip-flop circuits FF02 and FF03, and these jitters are each defined to be an absolute value JTR. It is noted that clock jitter JTR is a value per one cycle TK of the clock signal.
A skew MRG is defined to be the sum of jitter component JTR and clock skew uncertain factor SKWET.
Each of logic circuits LG1 and LG2 needs to perform a predetermined logic processing on the signal applied thereto and to transfer the resultant signal to the flip-flop at the next stage within a period of one cycle TK of clock signal CLK0.
FIG. 12 shows a time period (logic delay time) L which each of logic circuits LG1 and LG1 can use within one cycle period of clock signal CLK. Referring to FIG. 12, a period of one cycle TK of clock signal CLK covers output delay time TPD, signal logic delay time L of a logic circuit, jitter JTR, clock skew uncertain factor SKWET, setup time SUP of the flip-flop in the next stage, and clock skew fixed factor SKW of the flip-flop at the next stage. Jitter JTR indicates the magnitude of the changing range of the phase of the trigger edge (rising edge) of clock signal CLK.
In FIG. 12, therefore, it is necessary that each of logic circuits LG1 and LG2 satisfies the following setup conditional expressions:
L01xe2x89xa6TKxe2x88x92TPD01xe2x88x92SUP02+SKW01xe2x88x92SKWETxe2x88x92JTRxe2x80x83xe2x80x83(1); and
L02xe2x89xa6TKxe2x88x92TPD02xe2x88x92SUP03+SKW02xe2x88x92SKWETxe2x88x92JTRxe2x80x83xe2x80x83(2).
As for the hold time, logic delay time L01 and L02 of respective logic circuits LG1 and LG2 need to satisfy the following hold conditions since it is necessary to prevent the output signal of a flip-flop circuit from changing within the hold time of the flip-flop circuit at the next stage:
LH01xe2x89xa7HLD02xe2x88x92TPDH01+SKWH01+SKWETHxe2x80x83xe2x80x83(3); and
LH02xe2x89xa7HLD03xe2x88x92TPDH02+SKWH02+SKWETHxe2x80x83xe2x80x83(4).
The reason why no jitter JTR appears in the above hold conditional expressions is that a jitter occurs in each clock signal and the jitter components of the respective clock signals cancels out one another.
If LSI manufacturing process variations are considered, in general, it is often to use different values between the delay time used for the setup conditions and that used for the hold conditions. This is done for the following reasons. In a setup conditional expression, the case of the setup time being longer has to be taken into account. In a hold conditional expression, the case of the minimum hold time has to be taken into account in view of the conditions under which the flip-flop circuit in the next stage propagates a signal at the highest rate.
Therefore, by attaching symbol xe2x80x9cHxe2x80x9d to the ends of the corresponding reference symbols of the respective parameters under the setup conditions related to delay time, it is indicated that the parameters are those for the hold conditions. The logical delay time and the output delay time indicating the delay of the output of the flip-flop circuit relative to the rise of the clock signal are denoted by LH and TPDH, respectively. In addition, clock skews are in some cases considered under different conditions, as well. Therefore, by attaching symbol xe2x80x9cHxe2x80x9d to the end of the reference symbols related to the clock skews for the setup conditions, respectively, it is indicated that the parameters are those for the hold conditions.
In expressions (1) to (4), a part of or all of the fixed factors such as layout dependent process variations are in some cases required to be considered in clock skew uncertain factor SKWET, if they cannot be accurately calculated or there are restrictions on a CAD (computer-aided design) tool. For example, if a certain constant value is used for the clock skew between arbitrary flip-flop circuits due to the restrictions on the CAD tool, it is required to set the fixed factors SKW01 and SKW02 of the clock skew to 0 and to contain the maximum clock skew in the uncertain factor SKWET of the clock skew. In contrast, if variations due to the power supply voltage change, temperature change or the like can be accurately calculated or controlled, a part of or all of clock skew uncertain factor SKWET and jitter JTR can be considered in each of clock skew fixed factors SKW01 and SKW02 in some cases.
The following is defined for the variations of the uncertain factor:
SKWET+JTR=MRG.
Under this definition, above-stated setup conditional expressions (1) and (2) are modified as follows:
L01xe2x89xa6TKxe2x88x92TPD01xe2x88x92SUP02+SKW01xe2x88x92MRGxe2x80x83xe2x80x83(5); and
L02xe2x89xa6TKxe2x88x92TPD02xe2x88x92SUP03+SKW02xe2x88x92MRGxe2x80x83xe2x80x83(6).
If only the maximum clock skew in an entire clock distribution system is considered for the clock skews, the clock skew maximum value is included in uncertain factor MRG, whereby setup conditional expressions (5) and (6) can be modified as follows:
L01xe2x89xa6TKxe2x88x92TPD01xe2x88x92SUP02xe2x88x92MRGxe2x80x83xe2x80x83(7); and
L02xe2x89xa6TKxe2x88x92TPD02xe2x88x92SUP03xe2x88x92MRGxe2x80x83xe2x80x83(8).
Conditional expressions (7) and (8) are normally used when a pipeline is designed using flip-flops. In conditional expressions (5) and (6), a clock skew is calculated for each clock signal propagation path individually and logic circuits are designed according to the respective individual calculated values. In conditional expressions (7) and (8), all the paths (pipeline stages) are designed according to the maximum clock skew. Therefore, there exists a path (pipeline stage) to which longer logic delay time L than the logic delay time of an actual logic circuit is allocated between certain flip-flops.
From expressions (5) and (6), the condition for logic delay time L1+L2 between two pipeline stages is expressed as follows:
L01+L02xe2x89xa62xc2x7TKxe2x88x92TPD01xe2x88x92TPD02xe2x88x92SUP02xe2x88x92SUP03+SKW01+SKW02xe2x88x922xc2x7MRGxe2x80x83xe2x80x83(9).
If the clock skew fixed factor between flip-flop circuits FF01 and FF03 is defined as SKWA as shown in FIG. 9, this clock skew fixed factor SKWA can be regarded as the sum of the clock skew fixed factors of the respective pipeline stages. Namely, the following expression is defined:
SKW01+SKW02=SKWA.
If using this conditional expression, expression (9) can be modified as follows:
L01+L02xe2x89xa62xc2x7TKxe2x88x92TPD01xe2x88x92TPD02xe2x88x92SUP02xe2x88x92SUP03+SKWAxe2x88x922xc2x7MRGxe2x80x83xe2x80x83(10)
xe2x89xa62xc2x7TKxe2x88x92TPD01xe2x88x92TPD02xe2x88x92SUP02xe2x88x92SUP03+SKWAxe2x88x922xc2x7(SKWET+JTR).
If the average delay time till the output of a flip-flop from the clock input of the flip flop is defined as Tpd and the average setup time of the flip-flops is defined as Sup, then the average value of the permissible maximum logic delay time between the two pipeline stages can be considered as follows:
L01+L02=2xc2x7TKxe2x88x922Tpdxe2x88x922xc2x7Sup+SKWxe2x88x922xc2x7MRGxe2x80x83xe2x80x83(11).
FIG. 13 is a schematic diagram showing the configuration of a three-stage pipeline using flip-flops. In FIG. 13, the three-stage pipeline includes flip-flop circuits FF11 to FF14 which transfer signals applied thereto synchronously with clock signals CLK11 to CLK14, respectively, a logic circuit LG11 which performs a logic processing on the signal/data received from flip-flop circuit FF11 and transfers the resultant signal/data to flip-flop circuit FF12, a logic circuit LG12 which performs a logic processing on the signal/data received from flip-flop circuit FF12 and transfers the resultant signal/data to flip-flop circuit FF13, and a logic circuit LG13 which performs a logic processing on the signal/data received from flip-flop circuit FF13 and transfers the resultant signal/data to flip-flop circuit FF14.
For flip-flop circuit FF11, output delay time TPD11, setup time SUP11, and hold time HLD11 are defined. For flip-flop circuit FF12, output delay time TPD12, setup time SUP12, and hold time HLD12 are defined. For flip-flop circuit FF13, output delay time TPD13, setup time SUP13, and hold time HLD13 are defined. For flip-flop circuit FF14, output delay time TPD14, setup time SUP14, and hold time HLD14 are defined.
For clock signals CLK11 to CLK14 applied to flip-flop circuits FF11 to FF14, respectively, uncertain factor MRG of the clock skew is defined.
Clock skew fixed factor SKW11 exists between clock signals CLK12 and CLK11, clock skew fixed factor SKW12 exists between clock signals CLK12 and CLK13, and clock skew fixed factor SKW13 exists between clock signals CLK13 and CLK14. Clock skew fixed factor SKWA exists between clock signals CLK14 and CLK11 to flip-flop circuits FF14 and FF11, respectively.
In the three-stage pipeline shown in FIG. 13, if logic circuits LG11, LG12 and LG13 have logic delay time L11, L12 and L13, respectively, logic delay time L11 to L13 is required to satisfy the following setup conditional expressions and the following hold conditional expressions as in the case of the two-stage pipeline stated above.
L11xe2x89xa6TKxe2x88x92TPD11xe2x88x92SUP12xe2x88x92SKW11xe2x88x92MRGxe2x80x83xe2x80x83(12);
L12xe2x89xa6TKxe2x88x92TPD12xe2x88x92SUP13xe2x88x92SKW12xe2x88x92MRGxe2x80x83xe2x80x83(13);
L13xe2x89xa6TKxe2x88x92TPD13xe2x88x92SUP14xe2x88x92SKW13xe2x88x92MRGxe2x80x83xe2x80x83(14);
LH11xe2x89xa7HLD12xe2x88x92TPDH11+SKWH11+SKWETHxe2x80x83xe2x80x83(15);
LH12xe2x89xa7HLD13xe2x88x92TPDH12+SKWH12+SKWETHxe2x80x83xe2x80x83(16); and
LH13xe2x89xa7HLD14xe2x88x92TPDH13+SKWH13+SKWETHxe2x80x83xe2x80x83(17).
In expressions (15) to (17), the logic delay times of logic circuits LG11 to LG13 for the hold conditions are respectively denoted by reference symbols LH11 to LH13. Likewise, the output delay times of flip-flop circuits for the hold conditions are denoted by reference symbols TPDH11 to TPDH13, respectively. Likewise, as for the clock skew fixed factors, the clock skews for the hold conditions are denoted by reference symbols SKWH11 to SKWH13 and SKWETH, respectively.
In the above expressions, MRG is given by the sum of jitter JTR and clock skew uncertain factor SKWET as in the case of the two-stage pipeline. The reason why the jitter component is not considered in the hold conditional expressions is that a jitter similarly occurs to each clock signal and the jitters cancels out one another under the hold conditions as in the case of the two-stage pipeline.
In addition, clock skew fixed factor SKWA between flip-flop circuits FF14 and FF11 can be regarded as the sum of clock skew fixed factors SKW11, SKW12 and SKW13. Therefore, from expressions (12) to (14), the condition for logic delay time L11+L12+L13 between the three pipeline stages is expressed as follows:
L11+L12+L13xe2x89xa63xc2x7TKxe2x88x92TPD11xe2x88x92TPD12xe2x88x92TPD13xe2x88x92SUP12xe2x88x92SUP13xe2x88x92SUP14xe2x88x92SKWAxe2x88x923xc2x7MRGxe2x80x83xe2x80x83(18).
If the average delay time of the outputs of the flip-flops relative to input of the associated clock signals of the flip-flops is defined as Tpd and the average setup time of the flip-flops is defined as Sup, then the average permissible maximum logic delay time between the three pipeline stages can be regarded as follows:
L11+L12+L13=3xc2x7TKxe2x88x923xc2x7Tpdxe2x88x923xc2x7Sup+SKWAxe2x88x923xc2x7MRGxe2x80x83xe2x80x83(19).
From conditional expressions (11) and (19), it is appreciated that if a pipeline is designed using flip-flops, it is necessary to consider output delay time Tpd, clock skew uncertain factor MRG and setup time Sup by as many as the number of pipeline stages included between arbitrary flip-flops.
With the improvement of the operating frequency of LSI, a clock cycle becomes shorter. In addition, with the high integration and miniaturization of transistors and interconnections, the influence of process variations becomes greater. Accordingly, the ratio of uncertain factors, such as skews and jitters, in the clock cycle increases. Further, as the operating frequency increases, it has become more difficult to improve delay time TPD of the output of a flip-flop from the clock input of the flip-flop and setup time SUP of the flip-flop. Therefore, the influence of output delay time TPD, clock skew uncertain factor MRG and setup time SUP on the logic delay time increases, thereby making it difficult to design a pipeline and making it impossible to optimally design a pipeline which operates at high speed.
It is an object of the present invention to provide a method of designing a semiconductor integrated circuit device allowing easy designing of a pipeline which operates at high speed.
It is another object of the present invention to provide a method of designing a pipeline, capable of decreasing the influence of the operating parameters, clock skews and the like of flip-flop circuits.
It is still another object of the present invention to provide a semiconductor integrated circuit device which includes a pipeline optimally designed to operate at high speed.
A method of designing a semiconductor integrated circuit device according to the present invention is a method of designing a semiconductor integrated circuit device which includes a pipeline including a plurality of flip-flop circuits each transferring a signal synchronously with a basic clock signal, and includes the steps of: designing the pipeline using the flip-flop circuits with the assumption that a cycle period of a transfer clock signal is given by a sum of a cycle of the basic clock signal and a gain time obtained by replacing a flip-flop circuit in the pipeline with latch circuits; setting the cycle period of the transfer clock signal to the cycle period of the basic clock signal to detect an error path in the designed pipeline; dividing the flip-flop circuit related to the error path into a plurality of latch circuits operating complementarily with each other and synchronously with the clock signal; and dividing a logic circuit related to the error path by the plurality of latch circuits such that a predetermined conditional inequality for signal propagation delay is satisfied for logic circuit stages related to the respective latch circuits, thereby rearranging the logic circuits.
A semiconductor integrated circuit device according to the first aspect of the present invention includes: a first flip-flop circuit transferring a received signal synchronously with a clock signal; a first latch circuit operating complementarily to the first flip-flop circuit and synchronously with the clock signal, and transferring and latching an applied signal; a first logic circuit arranged between the first flip-flop circuit and the first latch circuit, performing a logic processing on a signal applied from the first flip-flop circuit, and transferring the resultant signal to the first latch circuit; a second latch circuit operating complementarily to the first latch circuit and synchronously with the clock signal, and transferring and latching the applied signal; a second logic circuit arranged between the first latch circuit and the second latch circuit, performing a logic processing on the signal received from the first latch circuit, and transferring a resultant signal to the second latch circuit; a second flip-flop circuit operating complementarily to the second latch circuit and synchronously with the clock signal, and transferring the applied signal; and a third logic circuit arranged between the second latch circuit and the second flip-flop circuit, performing a logic processing on the signal from the second latch circuit, and transferring a resultant signal to the second flip-flop circuit. The first and second latch circuits and the first and second flip-flop circuits are arranged so as to satisfy the following conditions:
L1xe2x89xa6TKxe2x88x92TPDF1xe2x88x92SUPL1+SKW1xe2x88x92SKETxe2x88x92JTRxe2x80x83xe2x80x83(1);
L2xe2x89xa6TKxe2x88x92TPDL1xe2x88x92SUPL2+SKW2xe2x88x92SKETxe2x88x92JTRxe2x80x83xe2x80x83(2);
L3xe2x89xa6TKxe2x88x92TPDL2xe2x88x92SUPF2+SKW3xe2x88x92SKETxe2x88x92JTRxe2x80x83xe2x80x83(3);
L1+L2xe2x89xa6(1+HDY)xc2x7TKxe2x88x92TPDF1xe2x88x92SUPL2+SKW4xe2x88x92SKETxe2x88x92JTRxc2x7K1xe2x88x92THR1xe2x80x83xe2x80x83(4);
L2+L3xe2x89xa6(1+LDY)xc2x7TKxe2x88x92TPDL1xe2x88x92SUPF2+SKW5xe2x88x92SKETxe2x88x92JTRxc2x7K2xe2x88x92THR2xe2x80x83xe2x80x83(5);
L1+L2+L3xe2x89xa62xc2x7TKxe2x88x92TPDF1xe2x88x92SUPF2+SKWAxe2x88x92SKETxe2x88x92JTRxc2x7K3xe2x88x92THR1xe2x88x92THR2xe2x80x83xe2x80x83(6);
L1xe2x89xa7HLDL1xe2x88x92TPDFH1+SKWH1+SKETHxe2x80x83xe2x80x83(7);
L2xe2x89xa7HLDL2xe2x88x92TPDLH1+SKWH2+SKETHxe2x80x83xe2x80x83(8); and
L3xe2x89xa7HLDF2xe2x88x92TPDLH2+SKWH3+SKWETHxe2x80x83xe2x80x83(9).
In the above conditions, L1, L2 and L3 indicate logic delay time of the first, second and third logic circuits, respectively; TK indicates the cycle period of the basic clock signal; TPDF1 indicates a delay of a signal output of the first flip-flop circuit from the clock signal; TPDL1 and TPDL2 indicate delays of output signals of the first and second latch circuits relative to the clock signal; SKW1, SKW2 and SKW3 indicate skews of the clock signal for a clock signal applied to the circuit at a preceding stage, respectively; SKW4 indicates a skew of the clock signal applied to the second latch circuit for the clock signal applied to the first flip-flop circuit; SKW5 indicates the skew of the clock signal applied to the first latch circuit for the clock signal applied to the second flip-flop circuit; and SKWA indicates the skew of the clock signal applied to the second flip-flop circuit for the clock signal applied to the first flip-flop circuit; SUPL1, SUPL2 and SUPF2 indicate setup time of the first latch circuit, setup time of the second latch circuit, and setup time of the third latch circuit, respectively.
SKET indicates a fixed skew of the clock signal; JTR indicates a jitter of the clock signal for the clock signal of the circuit at the preceding stage; THR1 and THR2 indicate signal propagation delay time of the first latch circuit and signal propagation delay time of the second latch circuit, respectively, relative to the respective input clock signals; HDY and LDY indicate duties of the latching periods of the clock signal applied to the first and second latch circuits, respectively; K1, K2 and K3 indicate coefficients representing cycle dependency of the jitter; HLDL1 and HLDL2 and HLDF2 indicate hold time of the first latch circuit, the second latch circuit and the second flip-flop circuit for the clock signal, respectively; TPDFH1, TPDLH1 and TPDLH2 indicate delays of output signals of the first flip-flop circuit, the first latch circuit and the second latch circuit relative to the clock signal for the hold condition; SKWH1, SKWH2 and SKWH3 indicate skews of the clock signal for the clock signal applied to the circuit at the preceding stage for the hold condition; and SKETH indicates the fixed skew caused by the uncertain factor of the clock signal.
A semiconductor integrated circuit device according to the second aspect of the present invention includes: a first flip-flop circuit transferring an applied signal synchronously with a clock signal; a first logic circuit performing a logic processing on the signal from the first flip-flop circuit, and outputting the resultant signal; a first latch circuit operating complementarily to the first flip-flop circuit and synchronously with the clock signal, and transferring and latching an output signal of the first logic circuit; a second logic circuit performing the logic processing on the signal from the first latch circuit, and outputting the resultant signal; a second latch circuit operating complementarily to the first latch circuit and synchronously with the clock signal, and transferring and latching the output signal of the second logic circuit; a third logic circuit performing the logic processing on the output signal of the second latch circuit, and outputting the resultant signal; a third latch circuit operating complementarily to the second latch circuit and synchronously with the clock signal, and transferring and latching the output signal of the third logic circuit; a fourth logic circuit performing the logic processing on the output signal of the third latch circuit, and outputting the resultant signal; a fourth latch circuit operating complementarily to the third latch circuit and synchronously with the clock signal, and transferring and latching the output signal of the fourth logic circuit; a fifth logic circuit performing the logic processing on the output signal of the fourth latch circuit, and outputting the resultant signal; and a second flip-flop circuit operating in phase with the fourth latch circuit synchronously with the clock signal, and transferring the output signal of the fifth logic circuit. The logic delay time L1 to L5 of the first to fifth logic circuits, respectively, satisfy the following conditions:
L1xe2x89xa6TKxe2x88x92TPDF1xe2x88x92SUPL1+SKW1xe2x88x92MRGxe2x80x83xe2x80x83(1);
L2xe2x89xa6TKxe2x88x92TPDL1xe2x88x92SUPL2+SKW2xe2x88x92MRGxe2x80x83xe2x80x83(2);
L3xe2x89xa6TKxe2x88x92TPDL2xe2x88x92SUPL3+SKW3xe2x88x92MRGxe2x80x83xe2x80x83(3);
L4xe2x89xa6TKxe2x88x92TPDL3xe2x88x92SUPL4+SKW4xe2x88x92MRGxe2x80x83xe2x80x83(4);
L5xe2x89xa6TKxe2x88x92TPDL4xe2x88x92SUPF2+SKW5xe2x88x92MRGxe2x80x83xe2x80x83(5);
L1+L2xe2x89xa6(1+HDY)xc2x7TKxe2x88x92TPDF1xe2x88x92SUPL2xe2x88x92SKW21xe2x88x92MRGJ1xe2x88x92THR1xe2x80x83xe2x80x83(6);
L2+L3xe2x89xa6(1+LDY)xc2x7TKxe2x88x92TPDL1xe2x88x92SUPL3xe2x88x92SKW22xe2x88x92MRGJ2xe2x88x92THR2xe2x80x83xe2x80x83(7);
L3+L4xe2x89xa6(1+HDY)xc2x7TKxe2x88x92TPDL2xe2x88x92SUPL4xe2x88x92SKW23xe2x88x92MRGJ1xe2x88x92THR3xe2x80x83xe2x80x83(8);
L4+L5xe2x89xa6(1+LDY)xc2x7TKxe2x88x92TPDL3xe2x88x92SUPF2xe2x88x92SKW24xe2x88x92MRGJ2xe2x88x92THR4xe2x80x83xe2x80x83(9);
L1+L2+L3xe2x89xa62xc2x7TKxe2x88x92TPDF1xe2x88x92SUPL3xe2x88x92SKW31xe2x88x92MRGJ3xe2x88x92THR1xe2x88x92THR2xe2x80x83xe2x80x83(10);
L2+L3+L4xe2x89xa62xc2x7TKxe2x88x92TPDL1xe2x88x92SUPL4xe2x88x92SKW32xe2x88x92MRGJ3xe2x88x92THR2xe2x88x92THR3xe2x80x83xe2x80x83(11);
L3+L4+L5xe2x89xa62xc2x7TKxe2x88x92TPDL2xe2x88x92SUPF2xe2x88x92SKW33xe2x88x92MRGJ3xe2x88x92THR3xe2x88x92THR4xe2x80x83xe2x80x83(12);
L1+L2+L3+L4xe2x89xa6(2+HDY)xc2x7TKxe2x88x92TPDF1xe2x88x92SUPL4xe2x88x92SKW41xe2x88x92MRGJ4xe2x88x92THR1xe2x88x92THR2xe2x88x92THR3xe2x80x83xe2x80x83(13);
L2+L3+L4+L5xe2x89xa6(2+LDY)xc2x7TKxe2x88x92TPDL1xe2x88x92SUPF2xe2x88x92SKW42xe2x88x92MRGJ5xe2x88x92THR2xe2x88x92THR3xe2x88x92THR4xe2x80x83xe2x80x83(14);
L1+L2+L3+L4+L5xe2x89xa63xc2x7TKxe2x88x92TPDF1xe2x88x92SUPF2xe2x88x92SKW51xe2x88x92MRGJxe2x88x92THR1xe2x88x92THR2xe2x88x92THR3xe2x88x92THR4xe2x80x83xe2x80x83(15);
L1xe2x89xa7HLDL1xe2x88x92TPDFH1+SKWH1+MRGHxe2x80x83xe2x80x83(16);
L2xe2x89xa7HLDL2xe2x88x92TPDLH1+SKWH2+MRGHxe2x80x83xe2x80x83(17);
L3xe2x89xa7HLDL3xe2x88x92TPDLH2+SKWH3+MRGHxe2x80x83xe2x80x83(18);
L4xe2x89xa7HLDL4xe2x88x92TPDLH3+SKWH4+MRGHxe2x80x83xe2x80x83(19); and
L5xe2x89xa7HLDF2xe2x88x92TPDLH4+SKWH5+MRGHxe2x80x83xe2x80x83(20).
In the above conditions, TK indicates the cycle period of the basic clock signal; TPDF1 indicates a delay time of a signal output of the first flip-flop circuit relative the clock signal; TPDL1 to TPDL4 indicate delays of output signals of the first to fourth latch circuits relative to a trigger edge of the clock signal; SUPL1 to SUPL4 indicate setup time of the first to fourth latch circuits for the clock signal; SUPF2 indicates the setup time of the second flip-flop circuit for the clock signal; SKW1 to SKW5 indicate skews of the clock signal for a clock signal applied to a circuit at the preceding stage; SKW21 to SKW24 indicate skews of clock signals for consecutive two stages of logic circuits of the first to fifth logic circuits; SKW31 to SKW33 indicate skews of clock signals for consecutive three stages of logic circuits of the first to fifth logic circuits; SKW41 and SKW42 indicate skews of clock signals of the first to fifth logic circuits for consecutive four stages of logic circuits; SKW51 indicates the skew of the clock signal applied to the second flip-flop circuit for the clock signal applied to the first flip-flop circuit; THR1 to THR4 indicate signal propagation delay time of the first to fourth latch circuits; HDY indicates a duty of the clock signal in a latching period of each of the first and third latch circuit; LDY indicates the duty of the clock signal in the latching state of each of the second and fourth latch circuit; MRG indicates a margin of the clock signal for a component including a jitter; MRGJ1 to MRGJ5 indicate margins for the clock signal with cycle dependency of the jitter taken into account; HLDL1 to HLDL4 indicate hold time of the first to fourth latch circuits for the clock signal, respectively; HLDF2 indicates the hold time of the second flip-flop circuit for the clock signal; TPDF1 indicates the delay of the output signal of the first flip-flop circuit from the trigger edge of the clock signal for the hold condition; TPDLH1 to TPDLH4 indicate the delays of output signals of the first to fourth latch circuits relative to the trigger edge of the clock signal; SKWH1 to SKWH5 indicate the skews of the clock signal for the clock signal applied to the circuit at the preceding stage for the hold conditions; and MRGH indicates the margin for the clock signal for the hold conditions.
By replacing a flip-flop circuit by a pair of complementarily operating latch circuits, it is possible to replace the output delay time of the flip-flop circuit, clock skews and the like by the data through time of the latch circuits. It is thereby possible to set the permissible maximum logic delay time of the pipeline stage of interest longer and to mitigate the conditions on the arrangement of the logic circuits.
In addition, since the inequalities are used as the conditional expressions, it is possible to provide an allowance for the arrangement position of each latch circuit when arranging the latch circuits, resulting in easy division of the logic circuit.
Furthermore, by dividing the logic circuit by the latch circuits, a path having a margin in logic delay time is formed. Therefore, by rearranging the circuits on this path, it is possible to reduce a circuit area.
Moreover, by arranging such a pipeline in the semiconductor integrated circuit device, it is possible to achieve a semiconductor integrated circuit device which stably operates synchronously with a high-speed clock signal.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.